1. Field of the Invention
The present invention relates generally to computer systems. More particularly, the present invention relates to memory systems.
2. Description of the Background Art
In today's computer industry, dynamic random access memories (DRAMs) are one of the dominant memory technologies. DRAMs are the preferred choice for large main memories because they are inexpensive, fast and consume little power. DRAMs are typically manufactured in discrete semiconductor packages having different input/output (I/O) data widths of, for example, sixteen, thirty-two, or sixty-four, or more data bits.
The number of data bits that a computer can simultaneously address and manipulate, i.e., the computer bus width, is typically much larger than that commonly available with DRAMs. To accommodate these bus widths, groups of DRAMs are typically packaged together to form memory modules, such as, for example, DIMMs (Dual In-line Memory Modules) and other types of memory modules.
FIG. 1A shows a side view of a conventional memory system 100 with two DIMM modules. The memory system 100 includes a CPU or memory controller 102 affixed to a motherboard 106 and two dual in line memory modules 108a and 108b. The two memory modules 108a–b shown each includes N memory devices 112 connected in parallel. Assuming for purposes of discussion that N is equal to eighteen, the eighteen memory devices 112a–N on each memory module 108a and 108b are connected to the memory controller 102 by a data bus 114, which includes board trace portions 116, a connectors 118 and a module trace portions 120.
FIG. 1B shows a block diagram of the memory structure of the memory modules of the memory system 100 shown in FIG. 1A. In FIG. 1B, the data bus is 72 bits wide where 64 bits are used for data and 8 bits are used for error correction. Each of the eighteen memory devices on the memory module 108a–b is 4 bits. The eighteen memory devices are connected in parallel so that for each memory operation, the output onto the data bus 114 is 72 bits wide.
FIG. 1C shows a clock pulse for reading or writing to a memory location of the memory system 100 shown in FIG. 1A. The memory controller 102 reads a single word or memory location from a single memory module at a time. Assuming a single data rate (SDR) system and a read operation, the memory location in memory module 108 having the address 000000 is read at the clock edge t1. The contents of the memory location is 72 bits wide. No memory operation occurs at clock edge t2. A second memory location having the address location 000001 in memory module 108 is read at the clock edge t3.
FIG. 2A shows a side view of a conventional memory system 200 having eight DIMM modules. Similar to the configuration shown In FIG. 1A, the memory system 200 shown in FIG. 2A includes a CPU or memory controller 202 affixed to a motherboard 206. However, this configuration includes eight dual in line memory modules 208a–h instead of the two DIMMs 108a–b shown in FIG. 1A. The eight memory modules 208a–h shown each includes N memory devices 212, The memory controller 202 is connected to the eight memory modules 208a–h by a data bus 214, which includes board trace portions 216, connectors 218 and module trace portions 220.
FIG. 2B shows a block diagram of the memory structure of the memory system 200 shown in FIG. 2A. In the system shown, the data bus is 144 bits wide where 128 bits are used for data and 16 bits are used for error correction. Preferably each memory module Includes eighteen memory devices (N=18), each memory device being 4 bits wide. For each memory module, the memory devices are connected in parallel. Data is read from two memory modules simultaneously, so that for each memory operation, the output onto the data bus 214 is 144 bits wide.
FIG. 2C shows a clock pulse for reading or writing to a memory location of the memory system 200 shown in FIG. 2A. The memory controller 202 reads a single word or memory location from a single memory module at a time. Assuming a double data rate (DDR) system and a memory read operation, the memory location in memory module 208a having the address 000000 and the memory location in memory module 208e having the address 000000 are both read simultaneously at the clock edge t1. A second memory location in memory module 208a having the address location 000001 and a second memory location having the address 000001 in memory module 208e are both read simultaneously at the clock edge t2.
The above-discussed relatively simple memory systems are merely illustrative examples discussed for background purposes. There are numerous other memory system configurations, some much larger and more complex than those discussed above. With the ubiquity of memory systems in computer systems, improvements in the methods and apparatus for utilizing and maintaining such memory systems are highly desirable.